It is known to employ a DPLL locked to a reference signal, for example a primary reference clock signal, to drive a hardware digitally controlled oscillator DCO (HDCO) generating the output clock signal. The reference signal is sampled at a sampling rate fsamp and fed into a DPLL comprising a phase comparator 12, a loop filter 14, and a software digitally controlled oscillator (SDCO) 18. The interrupt or sampling rate of the DPLL is the same as the sampling rate fsamp of the reference signal.
The loop filter generates an error value Δf for the SDCO, which error value Δf is also used to control the HDCO, which HDCO is essentially a modulo n counter that generates an output clock pulse on each rollover of the counter.
A schematic diagram of a prior art DPLL 10 running at the sampling rate fsamp is shown in FIG. 2. The reference input value ref, which is a sampled version of the reference clock signal, is applied to the phase comparator 12, the output of which is applied to the loop filter 14, which in turn outputs frequency error value Δf. This error value is applied to a multiplier-by-N 16, which provides a control input to the SDCO 18 whose output provides the second input to the phase comparator 12.
The output of the loop filter 14 is also applied to handoff block 20, which provides the input to the HDCO 22 generating the output clock signal clk. As noted the HDCO 22 is typically in the form of a modulo n counter, wherein the value loaded in the counter determines phase and the addend determines frequency.
Since the HDCO 22 generates the output clock signals clk, it runs at a rate fs that is N times faster than the sampling rate fsamp, where N is typically a large number. For example, for a sampling rate of 3.5 KHz, fs might be 200 MHz, in which case N=57344. The purpose of the multiplier-by-N 16 is to maintain synchronism with the HDCO 22 as explained with reference to FIG. 3.
An equivalent circuit for the structure of FIG. 2 is shown in FIG. 3 wherein the handoff block 20 is shown as a sample-hold register 24, which upsamples the data by N. The high rate domain running at clock rate fs is separated from the low rate domain running at clock rate fsamp by the dashed line 9. All the components above the dashed line run at the high rate fs, and all the components below the dashed line 9 run at the low rate fsamp, although as will be explained in more detail below the action of multiplier 16 in FIG. 2, shown as in dashed lines as its equivalent in FIG. 3, is to simulate the effect of running at the high rate fs even though the SDCO is actually running at the low rate fsamp.
In FIG. 3 the frequency control value Δf is upsampled and held by sample-hold register 24 for the duration of N clock cycles at the high rate fs, which is the same as one clock cycle at the low rate fsamp.
In order to achieve upsampling, a sample at the low sampling rate fsamp is loaded into the sample-hold register 24 and repeatedly output for N clock cycles at the high sampling rate fs as represented by the symbol ↑ N.
On the next clock cycle at the low rate fsamp, the next sample is loaded in to the sample-hold register 24, and so on. As a result, during one clock cycle of the DPLL 10, the HDCO 22 will be shifted by a frequency N*Δf. Thus to maintain synchronism between the SDCO 18 and the HDCO 22, the input control frequency to the SCDO 18 is multiplied by N. This operation, namely multiplying by N, is the equivalent to holding the sample Δf for N clock cycles at the high rate in sample-hold register 26 by the upsampling of sample-hold register 26, updating the frequency by Δf for each clock cycle at the higher rate by SDCO 18, and downsampling by N downstream of the SDCO 18 in downsampler 30. The result will be the same in both FIG. 2 and FIG. 3 in that that during one clock cycle at the rate fsamp, the SDCO 18 will be shifted by N*Δf and thus maintain synchronism with the HDCO 22. Thus, it will be appreciated that in FIG. 3, the function sample-hold register 26 and downsampler 30 shown in the equivalent circuit is in the real-world performed by the multiplier-by-N 16 in FIG. 2.
A well-known general problem arises as a result of the upsampling process of sample-hold register 26 as shown in FIG. 1. Spectrum images are created in the high frequency bands on either side of the desired signal. In order to remove the spectrum images a low-pass filter is required.
In general terms, upsampling from a low rate to a high rate N times higher than the low rate involves outputting each sample once at the high rate at the start of each low-rate clock cycle, and outputting zero values for the remaining N−1 clock high-rate clock cycles of the current low-rate clock cycle. In this case, however, the sample-hold register 24 does not output N−1 zero values after the current sample value has been output at the high rate, but instead continues to output the current sample until the end of the current-low rate clock cycle. The net result is that the current sample is output N times at the high rate during each low-rate clock cycle. This result is equivalent to passing the raw upsampled data, wherein the data is stuffed with N−1 zeros following each sample, through a FIR filter containing N values that are all “1”. Such a filter is a zero-order FIR filter. Consequently, the sample-hold register 24 is equivalent to a combined upsampler and zero-order low pass filter, and thus serves as an anti-image filter. Similar reasoning applies to the sample-register 26 except of course in this case, the sample-hold register 26 is virtual, rather than real since it only appears in the equivalent circuit for the multiplier-by-N 16.
The anti-imaging filter frequency response for a zero-order low-pass FIR filter is:sin(πfN/fs)/(N*sin(πf/fs))
where fs is HDCO system clock and N is the ratio between system clock and SDCO sampling clock (N=fs/fsamp). The HDCO has a phase transfer function of
            H      dco        ⁡          (      Z      )        =      1          1      -              Z                  -          1                    
which behaves like a low pass filter for phase noise.
The closed loop frequency response of the DPLL, which can be obtained from FIG. 2, is:
      H    ⁡          (      z      )        =                    H        l            ⁡              (                  Z                      -            1                          )                    1      +                        H          l                ⁡                  (                      Z                          -              1                                )                    -              Z                  -          1                    
where Hl(Z−1)=N*Filter, and Filter is the transfer function of the loop filter 14.
FIG. 4 shows simulated example using a zero-order low-pass FIR filter for fs=200 MHz and N=57344 (sampling frequency fsamp=3.5 KHz) with 100 Hz in-band wander noise. It will be seen that there are still significant harmonics, which manifest themselves as phase noise. The first harmonic for 100 Hz in-band tone is at 3.5 KHz+/−100 Hz, which has a magnitude about 60 dB below the tone value at 100 Hz. In this example there is a 60 dB reduction for every doubling of the sampling rate. The zero-order anti-image filter and the HDCO frequency response contribute equally to the 60 dB harmonic reduction (i.e. 30 dB each).